Job description
About InnoPhase, Inc.
INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications. To learn more about InnoPhase, visit www.innophaseinc.com.
As a Principal SOC Architect, you will be working in a design engineering team in SOC requirement and architecture definition/design for 5G ORAN in MIMO applications for both RU and DU.
InnoPhase offers several office locations in CA and a hybrid remote/office work environment providing an excellent balanced environment for a results-oriented individual committed to continuous improvement, learning, and collaboration.
Key Responsibilities:
- Define the system requirements for HW and SW partition for multi-core ARM & AXI/AHB bus architecture
- Collaborate with design engineers on microarchitecture and generate test vectors for design verification
- Collaborate within the SOC team and external customers to define the system requirements of the SERDES/10GE
- Work with design engineers to come up with comprehensive test plans and debug issues.
- Design & Integrate IP models at SOC level
- Conduct C/C++ and Matlab simulations to study system performance
- Generate reference model and test vectors in cycle true & bit accurate format for digital IP and SOC verification
- Work with digital design engineer to debug issues found in verification
- Participate in post-silicon bring-up, performance characterization and optimization
- Field testing and verify product performance using lab instruments
Job Requirements
- PhD with 3+ years of wireless system development experience or MSEE with 5+ years
- Good understanding of CPU bus architecture (AXI, APB, AHB), DMA, peripheral IP(USB, QSPI, JTAG)
- Proficient in System Verilog HDL/VHDL for design implementation and micro architecture
- In-depth understanding of JESD-204A, JESD-204A-C and IEEE 1394 requirements
- Good analysis/modeling skill with Matlab, Python or C/C++
- Clear communication and presentation skills with MS office tools
Benefits & Perks
- Market rate salary plus stock options
- Flexible hybrid work model
- Benefits include health insurance coverage and contribution from the employer, life and disability insurance, 401(k) matching, company-paid holidays, paid time off for vacation and sick, maternity/paternity paid leave, training reimbursement, and more.
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